Synchronous serial communication
Asynchronous serial communication
UART
- 비동기 직렬 통신을 해주는 장치(회로)
- 동기 통신, 비동기 통신
USART of AVR MCU
- high resolution baud rate generator(Clock Generator)
- full duplex operation(independent serial receive and transmit registers)
쓰기
- UDR(Transmit)에 대입
- Transmit Shift Register에 copy
- 전송 데이터 flag
읽기
- 새로운 데이터 확인(DREn pin)
- Receive Shift Register
- UDR(Receive)에 copy
Baud Rate Generation
- 오차가 2% 넘으면 통신 오류 발생 확률 증가
- **115200 bps에서는 오차를 줄이기 위해 (U2Xn = 1)**을 사용
Data Reception
- Asynchronous Normal mode vs Double Speed mode
- 분해능이 Normal mode(U2X0 = 0)가 좋지만, 통신 속도에 따라 오차가 발생하여 안 좋을 수도 있다.
- 7th-9th cycle 샘플링을 하면 노이즈 영향을 최소화 시킬 수 있다.
Framing
- Standard
- Start bit : 0 - idle(1) -> 0
- Stop bit : 1 - idle(1)상태로 만들기
- Optional parity bit
Registers about UART
Control and Status Registers
UCSRnA
- RXCn: USART Receive Complete
- UDR를 읽을 때 clear
- Receive Complete interrupt flag로 이용
- This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
- TXCn: USART Transmit Complete
- This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn)
- UDREn: USART Data Register Empty (1)
- 새로운 데이터 기록 가능(1)
- The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data
- FEn: Frame Error
- DORn: Data OverRun
- UPEn: USART Parity Error
- U2Xn: Double the USART Transmission Speed
- 115200bps에서는 1로 set 시켜야 통신 오류 감소
UCSRnB
- RXCIEn: RX Complete Interrupt Enable n
- TXCIEn: TX Complete Interrupt Enable n
- UDRIEn: USART Data Register Empty Interrupt Enable n
- RXENn: Receiver Enable n
- TXENn: Transmitter Enable n
UCSRnC
- UMSELn1:0 USART Mode Select
- UCSZn1:0: Character Size
Baud Rate Registers
UBRRnL and UBRRnH – USART Baud Rate Registers
- UBRRn 에 대입하면 compiler가 알아서 나눠준다.
Registers about UART
Control and Status Registers
UCSRnA
- RXCn: USART Receive Complete
- UDR를 읽을 때 clear
- Receive Complete interrupt flag로 이용
- This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
- TXCn: USART Transmit Complete
- This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn)
- UDREn: USART Data Register Empty (1)
- 새로운 데이터 기록 가능(1)
- The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data
- FEn: Frame Error
- DORn: Data OverRun
- UPEn: USART Parity Error
- U2Xn: Double the USART Transmission Speed
- 115200bps에서는 1로 set 시켜야 통신 오류 감소
UCSRnB
- RXCIEn: RX Complete Interrupt Enable n
- TXCIEn: TX Complete Interrupt Enable n
- UDRIEn: USART Data Register Empty Interrupt Enable n
- RXENn: Receiver Enable n
- TXENn: Transmitter Enable n
UCSRnC
- UMSELn1:0 USART Mode Select
- UCSZn1:0: Character Size
Baud Rate Registers
UBRRnL and UBRRnH – USART Baud Rate Registers
- UBRRn 에 대입하면 compiler가 알아서 나눠준다.
Registers about UART
Control and Status Registers
UCSRnA
- RXCn: USART Receive Complete
- UDR를 읽을 때 clear
- Receive Complete interrupt flag로 이용
- This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
- TXCn: USART Transmit Complete
- This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn)
- UDREn: USART Data Register Empty (1)
- 새로운 데이터 기록 가능(1)
- The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data
- FEn: Frame Error
- DORn: Data OverRun
- UPEn: USART Parity Error
- U2Xn: Double the USART Transmission Speed
- 115200bps에서는 1로 set 시켜야 통신 오류 감소
UCSRnB
- RXCIEn: RX Complete Interrupt Enable n
- TXCIEn: TX Complete Interrupt Enable n
- UDRIEn: USART Data Register Empty Interrupt Enable n
- RXENn: Receiver Enable n
- TXENn: Transmitter Enable n
UCSRnC
- UMSELn1:0 USART Mode Select
- UCSZn1:0: Character Size
Baud Rate Registers
UBRRnL and UBRRnH – USART Baud Rate Registers
- UBRRn 에 대입하면 compiler가 알아서 나눠준다.
Registers about UART
Control and Status Registers
UCSRnA
- RXCn: USART Receive Complete
- UDR를 읽을 때 clear
- Receive Complete interrupt flag로 이용
- This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
- TXCn: USART Transmit Complete
- This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn)
- UDREn: USART Data Register Empty (1)
- 새로운 데이터 기록 가능(1)
- The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data
- FEn: Frame Error
- DORn: Data OverRun
- UPEn: USART Parity Error
- U2Xn: Double the USART Transmission Speed
- 115200bps에서는 1로 set 시켜야 통신 오류 감소
UCSRnB
- RXCIEn: RX Complete Interrupt Enable n
- TXCIEn: TX Complete Interrupt Enable n
- UDRIEn: USART Data Register Empty Interrupt Enable n
- RXENn: Receiver Enable n
- TXENn: Transmitter Enable n
UCSRnC
- UMSELn1:0 USART Mode Select
- UCSZn1:0: Character Size
Baud Rate Registers
UBRRnL and UBRRnH – USART Baud Rate Registers
- UBRRn 에 대입하면 compiler가 알아서 나눠준다.
Registers about UART
Control and Status Registers
UCSRnA
- RXCn: USART Receive Complete
- UDR를 읽을 때 clear
- Receive Complete interrupt flag로 이용
- This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
- TXCn: USART Transmit Complete
- This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn)
- UDREn: USART Data Register Empty (1)
- 새로운 데이터 기록 가능(1)
- The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data
- FEn: Frame Error
- DORn: Data OverRun
- UPEn: USART Parity Error
- U2Xn: Double the USART Transmission Speed
- 115200bps에서는 1로 set 시켜야 통신 오류 감소
UCSRnB
- RXCIEn: RX Complete Interrupt Enable n
- TXCIEn: TX Complete Interrupt Enable n
- UDRIEn: USART Data Register Empty Interrupt Enable n
- RXENn: Receiver Enable n
- TXENn: Transmitter Enable n
UCSRnC
- UMSELn1:0 USART Mode Select
- UCSZn1:0: Character Size
Baud Rate Registers
UBRRnL and UBRRnH – USART Baud Rate Registers
- UBRRn 에 대입하면 compiler가 알아서 나눠준다.
Registers about UART
Control and Status Registers
UCSRnA
- RXCn: USART Receive Complete
- UDR를 읽을 때 clear
- Receive Complete interrupt flag로 이용
- This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
- TXCn: USART Transmit Complete
- This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn)
- UDREn: USART Data Register Empty (1)
- 새로운 데이터 기록 가능(1)
- The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data
- FEn: Frame Error
- DORn: Data OverRun
- UPEn: USART Parity Error
- U2Xn: Double the USART Transmission Speed
- 115200bps에서는 1로 set 시켜야 통신 오류 감소
UCSRnB
- RXCIEn: RX Complete Interrupt Enable n
- TXCIEn: TX Complete Interrupt Enable n
- UDRIEn: USART Data Register Empty Interrupt Enable n
- RXENn: Receiver Enable n
- TXENn: Transmitter Enable n
UCSRnC
- UMSELn1:0 USART Mode Select
- UCSZn1:0: Character Size
Baud Rate Registers
UBRRnL and UBRRnH – USART Baud Rate Registers
- UBRRn 에 대입하면 compiler가 알아서 나눠준다.
Data Transmit and Receive
Polling 방식
- UART가 수신한 데이터를 1byte씩 읽어오는 함수
- scanf 함수 내부에서 사용
int8_t uart_getch(void){
while(!(UCSR0A & _BV(RXC0))) ;
return UDR0;
}
- UART로 데이터를 1byte씩 전송하기 위한 함수
- printf 함수 내부에서 사용
void uart_putch(int8_t ch){
while(!(UCSR0A & _BV(UDRE0)));
UDR0 = ch;
}
Interrupt 사용 방식
- 데이터 수신
- 새로운 데이터 수신 시 RxCn flag가 1 → ISR 실행
ISR(USART0_RX_vect){
// (UDR0를 읽어 사용 or 다른 변수에 저장)
}
- 데이터 송신
- circular queue를 사용하여서 데이터 보내는 시간을 관리
- TxCn flag가 1 → Transmit Complete Interrupt 발생(Edge-triggered)
- UDREn flag가 1 → Data Register Interrupt 발생(Level-triggered)